Single Spin Wireless Architecture of nm Priority Resolver

Priority resolver is ubiquitous in digital logic circuits as it is frequently used to optimize large number of inputs into a minimum number of outputs. This particular circuit exclusively demonstrate manifestation of outputs, controlled by the priority of logic interventions of the inputs. CMOS Logic made circuits with higher number of inputs experiences an excessive power dissipation. On the other hand, Single Spin Logic (SSL) offers low power dissipation, high speed, high packing density in circuit design. It is a novel approach in device vicinity that involves the spin polarity of electron rather only the charge. Thus the authors motivated themselves to design SSL based priority resolver. This technical note presents a pragmatic view of priority resolver design using SSL.